In EEPROMs using floating gate memory cells, a memory cell is either in a low threshold voltage state or a high threshold voltage state. Typically, the low threshold voltage state is a zero or programmed state whereas the high threshold voltage state, is a one or erased state. Accordingly, the noise margin between a zero and a one is the difference between the low threshold voltage and the high threshold voltage. It has been discovered that this noise margin tends to improve as the memory cell is cycled between a zero and a one. The number of cycles for which improvement is obtained varies with the process involved, but typically range between 10 and 20. The noise margin remains essentially constant thereafter until a significantly greater number of cycles has occurred. The point at which degradation begins is also process dependent, but is typically about 10,000 times.
It is desirable from both the users' and the manfacturers' viewpoint to work with an EEPROM having substantially constant noise margin. In the prior art, however, there was no convenient way to cycle all of the cells in the array between a zero and a one. Typically, an entire array could be erased to the one state in a single operation but the zero state could be obtained by programming one word location, e.g., eight memory cells, at a time. Consequently, thousands of operations are required in order to cycle all of the cells in the array between a zero and a one a single time.